CONCURRENT ERROR-DETECTION CIRCUIT SYNTHESIS BASED ON BOOLEAN COMPLEMENT METHOD USING WEIGHT-BASED SUM CODE
The paper explores the use of weight-based sum code for concurrent error-detection circuits used in digital computing devices. The Boolean complement method is described. The authors give a brief overview of the use of uniform block codes in the synthesis of concurrent error-detection circuits by the Boolean complement method. It is noted that weight-based sum codes have not previously been used for this purpose. The application of the codes allows selecting the weight coefficients values when determining the coding method for a digital device with a known structure. The article describes the procedure of choosing the weight coefficients and the stages in synthesizing a concurrent error-detection circuit by the Boolean complement method. The use of weight-based sum code makes it possible to synthesize completely self-checking digital devices even in the cases when this cannot be achieved using other codes, for example, Berger, Bose-Lin or the standard duplication method.
Keywords: concurrent error-detection circuit; Boolean complement method; weight-based sum code; self-checking digital devices synthesis; calculation control
